1. Field of the Invention
The present invention relates to testing of nonvolatile, reprogrammable logic devices (PLDs). More particularly, the present invention relates to storing volatile data in a non-volatile cell array memory in a PLD.
2. The Background Art
PLDs are integrated circuit devices which contain gates or other general-purpose cells whose interconnections can be configured by programming to implement nearly any desired combinatorial or sequential function. FPGAs are well known in the PLD art. FPGAs generally include an array of general-purpose logic circuits, typically referred to as logic blocks, which can be programmed by programmable elements to implement virtually any logic function. The programmed logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements.
It is well known in the art that both volatile and non-volatile reprogrammable elements have been used to provide interconnection in FPGA devices. Volatile programmable elements are often a pass transistor controlled by a static random access memory (SRAM) cell. Reprogrammable SRAM based architectures are well known in the FPGA art. In an SRAM based reprogrammable FPGA, the programmable elements are typically passgates controlled by information stored in an SRAM configuration memory.
There are a variety of non-volatile reprogrammable memory devices known to those of ordinary skill in the art. These include floating gate transistors, and local charge storage MOS transistors such as floating trap MOS transistors, including SONOS or MONOS devices, and floating gate silicon nanocrystal MOS transistors. In known non-volatile memory based FPGAs, there are numerous examples of non-volatile memory cells that employ, either alone or in some arrangement, these non-volatile reprogrammable memory devices.
A floating gate transistor is an MOS based device having an unconnected or floating polysilicon layer disposed in a dielectric between the semiconductor surface and the gate of the MOS transistor. While there are a variety of known floating gate transistor technologies, in a floating gate transistor based FPGA, the floating gates are typically similar to those used in flash memories the operation of which is well known to those of ordinary skill in the art, but adapted for use in programmable arrays. Proposed floating gate transistor memory elements employed in programmable logic devices include electrically programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM), flash EEPROM, NOR flash and NAND flash.
To program the floating gate transistor, electrons are placed on the floating polysilicon layer, and to erase the floating gate memory cell, electrons are removed from the floating polysilicon layer. According to the particular floating gate transistor technology involved, electrons are placed onto the floating gate and removed from the floating gate by a combination of channel hot electron injection or Fowler-Nordheim tunneling and UV light, hot hole injection or Fowler-Nordheim tunneling, respectively. Each of these methods for placing and removing electrons on the floating require the gate, source, drain and substrate of the floating gate transistor to either be biased to voltages relative to one another or to float for a time sufficient to either program or erase the floating gate transistor.
As is well known in the art, a floating gate memory cell is programmed when sufficient electrons are placed on the floating polysilicon layer to prevent the MOS transistor of the floating gate memory cell from being turned on. The charged floating polysilicon layer opposes a voltage which, when applied to the gate of the floating gate memory cell would typically turn-on the MOS transistor of the floating gate memory cell. When these electrons are removed, a normal operating voltage applied to the gate of floating gate transistor will result in current flowing through the MOS transistor of the floating gate memory cell. It well known by and within the skill of those of ordinary skill in the art that the voltages required to program and operate a particular implementation of a floating gate transistor depend upon the particular geometries of the floating gate transistor employed. During a read operation, this current may then be sensed to determine whether a particular floating gate memory cell has been programmed.
In an n-channel floating gate silicon nanocrystal MOS transistor, a p-type region formed by a p-type semiconductor substrate or p-type well formed in a semiconductor substrate has a first n-type source/drain (S/D) region and a second n-channel source/drain region, and a lower silicon dioxide layer of typically about 20 to about 60 angstroms in thickness is disposed above the p-type region and a portion of the source and drain regions and, respectively, in a manner of forming an MOS transistor as is well known to those of ordinary skill in the art.
A layer of silicon nanocrystals typically having diameters of typically about 40 angstroms to about 100 angstroms and spaced apart by about 40 angstroms to about 60 angstroms is disposed above the lower silicon dioxide layer. The silicon nanocrystal layer forms a floating gate that traps charge as it is injected across the oxide layer and into the silicon nanocrystal layer. An upper layer of silicon dioxide of about 60 angstroms is formed over the silicon nanocrystal layer. A polysilicon or metal conductive control gate is disposed above the upper oxide layer. The upper oxide layer electrically isolates the conductive control gate from floating gate formed by the silicon nanocrystal layer.
In a floating gate silicon nanocrystal MOS transistor, charge is stored (trapped) in or removed from after being trapped in the silicon nanocrystals. Unlike a conventional floating gate transistor, where charge stored on the polysilicon conductor may flow freely in the polysilicon conductor, charge stored in a floating gate silicon nanocrystal MOS transistor is localized to the region of the floating nanocrystal material above the source or drain where it was originally placed during programming. Accordingly, a bit of information may be stored above each of the junctions of a nanocrystal based MOS transistor for a total of two bits. This two-bit charge storage is analogous to the two-bit charge storage provided by a floating trap MOS transistor such as SONOS or MONOS. To program a floating gate silicon nanocrystal MOS transistor device both channel hot electron injection and Fowler-Nordheim tunneling have been employed. To erase a floating trap MOS transistor device both Fowler-Nordheim tunneling and tunneling enhanced hot hole injection have been employed.
After an FPGA has been manufactured, the routing resources and logic resources must be tested to establish the correct function and reliability of the part. For instance, tests must establish the absence of undesired shorts or opens among the routing tracks and correct functioning of the logic, switches, and buffers. Presently, one known method of testing the FPGA is to identify, program, and verify some sufficient number of designs carefully chosen for this purpose. Each design is programmed into the FPGA and test vectors are then applied to the design to determine whether the various elements of the design are properly connected and functioning. This process is then repeated for each of the selected number of designs to be tested.
The time required to reprogram the non-volatile FGPA for each test design can be considerable, and may represent a significant portion of the cost of the tested integrated circuit die. In some instances, depending on the particular non-volatile memory cell, the amount of programming time required can be reduced with techniques such as the simultaneous writing of many bits. This is not always feasible, or may still not achieve an acceptable reduction. As a consequence, it would be desirable to find techniques for testing a non-volatile FGPA that reduce the number of times the non-volatile configuration memory must be programmed.
Techniques that allow multiple designs to be configured in a volatile fashion without completely reprogramming the non-volatile configuration memory would also be useful for other purposes, including rapid prototyping and dynamic reconfiguration a portion of a design during normal operation of the FPGA.